1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor.
2. Description of the Related Art
In the manufacturing of deep submicron devices, the level of integration is increased. Hence, line width, contact area and junction depth of all devices are reduced. To improve the quality of devices and to lower transmission delay due to an increase in electrical resistance and capacitor (RC-delay), silicide layers are usually formed over the MOS transistors. The silicide layers are formed over the polysilicon gate and the source/drain terminals so that contact resistance at these junctions is lowered. Since there is no need to perform photolithographic operation, the step of forming silicide layers over the terminals of MOS transistors is often referred to as a self-aligned silicide (Salicide) process. Materials for forming a self-aligned silicide layer include titanium silicide (TiSi.sub.x) and cobalt silicide (CoSi.sub.x). Because titanium silicide has the advantage of easy control during fabrication, it is one of the most frequently employed silicide materials.
Titanium silicide layer can be further classified structurally as being in a C49 high-resistance metastable phase (C49-TiSi.sub.2) or in a C54 low-resistance thermodynamically stable phase (C54-TiSi.sub.2). To form a titanium silicide layer, a first stage rapid thermal heating process is carried out so that titanium in a titanium layer reacts with silicon in a silicon layer. After the first stage thermal process, C49 phase titanium silicide and a small amount of C54 phase titanium silicide are formed. The unreacted titanium layer is removed, and then a second stage rapid thermal heating operation is carried out at an elevated temperature. In the second stage thermal operation, the high-resistance C49 phase titanium silicide within the titanium silicide layer is gradually transformed into a low-resistance C54 phase titanium silicide.
C49 phase titanium silicide has a low formation temperature but its electrical resistance is high. In contrast, C54 phase titanium silicide has a low electrical resistance but its formation temperature is high. In general, a rapid thermal process for transforming the high-resistance C49 phase titanium silicide in a titanium silicide layer into low-resistance C54 phase titanium silicide must be employed. Furthermore, in order to form a thick and uniform silicide layer, processing temperature must be raised or the period of heating must be extended.
As dimensions of the polysilicon gate are gradually reduced due to miniaturization, the formation temperature of the C54 phase titanium silicide is increased because of the narrow line effect. The narrow line effect refers to the increase in phase transformation temperature resulting from a decrease in line width.
In other words, as line width becomes smaller, temperature required to transform high-resistance C49 phase titanium silicide into low-resistance C54 phase titanium silicide is increased. However, raising the rapid thermal processing temperature to obtain C54 phase titanium silicide may result in some instability in the resulting silicide layer. Hence, too high a processing temperature is unsuitable for forming small dimensional devices. Moreover, reaction temperature is difficult to control and may result in lateral growth of the silicide layer. In addition, as the level of integration continues to increase and separation between neighboring devices continues to decrease, lateral growth can easily lead to bridging between a gate terminal and a source/drain terminal. To prevent such bridging, an upper limit to the temperature for forming a metal silicide layer must be set. However, this will result in an intensification of the narrow line effect. Hence, a higher resistance will be formed at the polysilicon gates.